Job Title

JD of Senior ASIC/SoC RTL Engineer/Lead – 5-10yrs 1) Expertise in SoC subsystem/IP design 2) Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog 3) In depth knowledge on RTL quality checks (Lint, CDC) 4) Knowledge of synthesis and low power is a plus 5) Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB) 6) Good understanding of timing concepts 7) Knowledge of one or more of the interface protocols a. PCIe b. DDR c. Ethernet d. I2C, UART, SPI 8) Expertise in setting up and using tools like a. Spyglass Lint/CDC b. Synopsys DC c. Verdi/Xcellium 9) Understanding of scripting languages like Make flow, Perl ,shell, python etc 10) Understanding of processor architecture and/or ARM debug architecture is a plus 11) Able to help and debug issues for multiple subsystems 12) Able to create/review design documents for multiple subsystems 13) Able to support physical design, verification, DFT and SW teams on design queries and reviews