Job Title

Principal Design Verification Engineer: SOC Focused [Experience Level 10+]BangaloreFounded in 2023,by Industry veterans HQ in California,US Location: Greater Bengaluru Area Company DescriptionWe are looking for exceptional talent and leadership to join , the world’s first company developing Agentic Silicon for powering the future of AI.Founded in 2023, our team consists of 90+ highly skilled engineers from leading companies such as Intel, Marvell, Nvidia, Qualcomm, Cisco, AMD, Apple etc. We have deep customer engagements across America, Europe, and Asia, and demonstrated functional prototypes to prove our concept and vision.Principal Design Verification Engineer: SOC Focused [Experience Level 10+] Job Description We are seeking a SoC Verification Engineer to work on end-to-end data-path verification for high-performance ARM-based SoCs. This role focuses on validating correctness, coherency, performance, and scalability of data movement across PCIe and CXL fabrics, from IP blocks through interconnect to CPUs and memory, at chip and multi-chip system levels.Validate PCIe/CXL Data path at full chip and multichip level.Validate CXL data flows, Host–device coherency interactions Validate cache coherency across multiple cores, agents, accelerators, across chip boundariesVerify the functionalities of Reset, Power, Error interaction with data path focus Execute SoC-level DV plans for data pathImplement system level stimulus for concurrent core/cache/dma/io traffic pathsImplement:UVM-based system tests including mid-transaction reset, contention scenarioScoreboards and data integrity checks under high throughput, concurrent trafficDebug complex failures using:WaveformsTransaction tracesFirmware interactionCollaborate with RTL, architecture, and firmware teams Required QualificationsExperience verifying ARM-based SoCsStrong knowledge of:PCIe protocol (transaction & data path focus)CXL (io/cache/mem)UCIE Understanding of cache coherency (CHI / ACE preferred)Proficiency in:SystemVerilog / UVMTransaction-level verificationSolid grasp of:AXI / NoC architecturesDMA engines and memory systems Preferred QualificationsMulti-chip / chiplet system experience Exposure to real workloads (storage, networking, AI accelerators)Contact:UdayMulya Technologiesmuday_bhaskar@/"Mining The Knowledge Community/"