Physical Design LeadLocations: BangaloreExperience: 10–16 Years (VLSI Physical Design)About the RoleWe are looking for a highly experienced Physical Design Lead to own top-level physical implementation and integration of large-scale SoC and ASIC platforms. In this role, you will drive hierarchical integration strategy from netlist to GDSII, ensuring world-class PPA (Power, Performance, Area) and signoff quality across complex, multi-block designs.You will operate at the center of architecture, RTL, IP, DFT, packaging, and signoff teams—leading execution, shaping methodology, and delivering first-pass silicon success on advanced technology nodes.What You’ll DoEnd-to-End Physical IntegrationOwn top-level hierarchical physical design from netlist through tapeoutDefine and drive floorplanning, partitioning, and integration strategy for large SoCsIntegrate CPUs, accelerators, memory subsystems, analog/hard macros, and third-party IPLead top-level placement, CTS, routing, and physical optimizationResolve congestion, cross-block interactions, and integration challengesTiming, Power & Signoff ExcellenceDrive top-level timing closure including complex inter-block pathsOwn power planning and power integrity (IR/EM) closureAddress signal integrity, noise, and crosstalk issuesEnsure readiness for:STAPhysical Verification (DRC/LVS)Reliability and signoffCross-Functional LeadershipPartner with RTL, architecture, IP, DFT, packaging, and signoff teamsProvide early physical feedback to influence micro-architecture decisionsReview block-level constraints, floorplans, and PD quality metricsAlign integration strategy with product performance and schedule goalsTechnical Ownership & MentorshipLead and mentor block-level PD teams across multiple design partitionsDefine scalable hierarchical PD flows and best practicesDrive methodology improvements for quality, runtime, and predictabilityLead design reviews and technical risk mitigationProgram ExecutionOwn top-level integration milestones and delivery commitmentsCommunicate risks, trade-offs, and status clearly to stakeholdersSupport customer reviews and tapeout readiness checkpointsRequired QualificationsBachelor’s or Master’s degree in Electrical/Electronics Engineering or related field10–16 years of hands-on experience in physical design and SoC integrationStrong expertise in hierarchical physical design of large SoCsDeep understanding of:Floorplanning & partitioningCTS & routingTiming closureIR/EM & signal integrityPhysical verification & signoffExtensive experience with industry tools such as:Cadence InnovusSynopsys ICC2PrimeTime / TempusStrong scripting skills in Tcl, Perl, and/or PythonProven leadership, communication, and execution skillsPreferred QualificationsExperience on advanced nodes (7nm, 5nm, 3nm, 2nm)Exposure to 2.5D/3D IC and advanced packaging technologiesPrior customer-facing or technical delivery ownershipExperience with very large multi-die or high-performance compute SoCsWhy You’ll Love This RoleOwn physical integration of next-generation silicon platformsInfluence architecture and product quality at massive scaleWork on cutting-edge process technologies and packaging innovationsLead complex designs that power AI, cloud, networking, and compute systemsAbout Us:Silicon Patterns is a specialized engineering services company with deep expertise in pre-silicon and post-silicon design and verification. We deliver end-to-end semiconductor and embedded system solutions covering RTL Design, SystemC Modeling, Emulation, Design Verification (DV), Physical Design (PD), Design for Testability (DFT), and Pre- & Post-silicon Validation — helping clients achieve faster, more reliable product development. Headquartered in Hyderabad, with offices in Bangalore and Raipur, and supported by our skilled engineering teams in Malaysia, we serve global clients through flexible engagement models like Time & Materials (T&M), Offshore Development Centers (ODC), Subcontracting, and Build-Operate-Transfer (BOT). Our expertise spans VLSI and Embedded Systems, with a strong focus on Wireless, IoT, and Automotive domains. We also work on advanced technologies including HBM3/3E workloads, AI/ML, GenAI/LLMs, and edge computing. At Silicon Patterns, we’re committed not only to technical excellence but also to maintaining a strong work-life balance for our teams because great engineering starts with well-supported people.Websitehttps:
Job Title
Lead Physical Design Engineer