Job Title

Role summaryWe are building a system that implements surface-code quantum error correction with a hardware-accelerated pipeline (multi-FPGA). We already have the FPGA architecture expertise in-house. This role is for a surface-code implementation specialist, someone who understands the surface code deeply and has practical experience with decoder implementations / syndrome-processing pipelines.You will be the person who makes the surface code “real” at the implementation level: clear algorithmic choices, concrete dataflows, executable reference models, and unambiguous specs that our FPGA team can implement and verify.What you’ll doOwn the surface-code implementation plan (algorithm → implementation)Define the full syndrome processing + decoding workflow for the chosen surface-code setupIdentify performance targets: cycle-level latency constraints, throughput requirements, scaling behaviorDecoder strategy + practical implementation detailsEvaluate or define a decoder approach suitable for real-time/streaming constraintsProvide implementation-ready descriptions (data structures, update rules, scheduling, approximations)Work with the FPGA architect on what belongs in FPGA vs host/control softwareCreate implementation artifacts the FPGA team can executeDetailed algorithm spec (state machines, message formats, boundary conditions, corner cases)Reference implementation in Python/C++ (or similar) to generate expected outputsTest vectors + golden models for verification (including fault/noise model assumptions)Support integration + validationDebug mismatches between reference model and hardware behaviorDefine success metrics (logical error rate targets, latency budget, resource scaling)Must-have qualifications (non-negotiable)Deep working knowledge of surface code QEC beyond textbook level (stabilizers, syndrome extraction, decoding, boundaries/defects or lattice surgery—depending on your approach)Hands-on implementation experience with at least one of:Surface-code decoder implementation (research prototype or product)Real-time syndrome processing pipelineHardware-aware acceleration work (FPGA/GPU/ASIC) for decoding or related graph problemsStrong engineering skills in Python and/or C++ for reference models, test generation, and performance experimentsAbility to write precise implementation specs that a hardware team can execute without ambiguityNice-to-have (strong plus)Familiarity with practical decoder families (examples: MWPM-style, union-find, belief propagation / weighted BP, or other practical variants)Comfort with hardware constraints: streaming dataflows, fixed-point reasoning, memory locality, pipeline schedulingPrior collaboration with FPGA/ASIC teams, including verification and bring-up realitiesOpen-source contributions, publications, or prior work demonstrating surface-code implementationWhat success looks likeA clear decoder/workflow choice with documented tradeoffsA validated reference model + test harness that produces golden outputsA complete “implementation map” for FPGA: inputs/outputs, message formats, timing assumptions, corner casesSmooth integration with our multi-FPGA system and measurable performance progressHow to applySend to rdumke@ :Resume/LinkedIn profileA short description of your most relevant surface code implementation workLinks to any code, papers, talks, or projects (optional but highly valuable)