Job Title

Senior DFT EngineerLocation: Bengaluru, IndiaExperience: 3–12 YearsRole Type: Full-time | Silicon EngineeringAbout the RoleWe are seeking a Lead Design-for-Test (DFT) Engineer to drive RTL-centric DFT architecture and execution for complex SoCs and subsystems used in high-performance compute, AI acceleration, and advanced connectivity platforms.You will own the complete DFT lifecycle — from RTL insertion strategy through pattern generation, simulation, and silicon-quality coverage closure — while partnering with design, physical implementation, and post-silicon teams to ensure first-pass success.This role is ideal for engineers who combine deep hands-on DFT implementation with system-level thinking and execution excellence. What You’ll DoLead RTL-level DFT architecture and implementation across full SoC and block/partition hierarchiesOwn DFT flows using Mentor Tessent across:Scan insertionMBISTOCC (on-chip clocking)EDT compression using ARM DFT flowDrive LEC (Logical Equivalence Check) at:RTL pre-DFT vs post-DFTRTL vs gate-level netlistsExecute pattern generation, retargeting, and simulation at block and SoC levelPerform zero-delay and timing-aware simulations using SDF back-annotationDrive coverage closure across stuck-at, transition, and memory faultsDevelop scan synthesis flows and timing constraints aligned with physical design requirementsPartner with PD teams to ensure timing-clean DFT insertionDebug test failures through simulation and silicon correlationMentor engineers and review DFT architecture across projectsInterested folks can share CV at ishitaanand@NP- within 60 days