Job Title

Lead DFT Engineer Location: Bengaluru, India Experience: 6–10 Years Role Type: Full-time | Silicon Engineering About the Role We are seeking a Lead Design-for-Test (DFT) Engineer to drive RTL-centric DFT architecture and execution for complex SoCs and subsystems used in high-performance compute, AI acceleration, and advanced connectivity platforms. You will own the complete DFT lifecycle — from RTL insertion strategy through pattern generation, simulation, and silicon-quality coverage closure — while partnering with design, physical implementation, and post-silicon teams to ensure first-pass success. This role is ideal for engineers who combine deep hands-on DFT implementation with system-level thinking and execution excellence. What You’ll Do Lead RTL-level DFT architecture and implementation across full SoC and block/partition hierarchies Own DFT flows using Mentor Tessent across: Scan insertion MBIST OCC (on-chip clocking) EDT compression using ARM DFT flow Drive LEC (Logical Equivalence Check) at: RTL pre-DFT vs post-DFT RTL vs gate-level netlists Execute pattern generation, retargeting, and simulation at block and SoC level Perform zero-delay and timing-aware simulations using SDF back-annotation Drive coverage closure across stuck-at, transition, and memory faults Develop scan synthesis flows and timing constraints aligned with physical design requirements Partner with PD teams to ensure timing-clean DFT insertion Debug test failures through simulation and silicon correlation Mentor engineers and review DFT architecture across projects Minimum Qualifications 6–10 years of hands-on DFT engineering experience in SoC environments Strong expertise in Mentor Tessent DFT tool flow Deep RTL-level implementation experience for: Scan MBIST OCC EDT compression (ARM DFT methodology) Proven experience across SoC and block/subsystem-level DFT Strong experience in: LEC flows (RTL ↔ post-DFT ↔ gate) Pattern generation, retargeting, and fault simulation Timing-aware simulation using SDF Coverage closure methodologies Solid understanding of scan synthesis and timing constraint development Strong RTL skills (Verilog/SystemVerilog) Bachelor’s or Master’s degree in Electrical Engineering or related field Preferred Qualifications Experience in advanced nodes (7nm and below) Post-silicon debug and yield learning exposure Strong scripting (TCL, Python) for flow automation Experience mentoring or leading small technical teams Must-Have Domain Knowledge SSN (Simultaneous Switching Noise) analysis awareness and mitigation within DFT strategies What Makes This Role Exciting Ownership of full DFT lifecycle — not just insertion Exposure to large, complex SoC architectures Influence silicon quality at production scale Work with industry-leading DFT methodologies Fast-paced FAANG-style engineering culture Your Impact Enable first-pass silicon success Achieve industry-leading test coverage Reduce test cost through smart compression strategies Build scalable RTL-first DFT frameworks About Us:Silicon Patterns is a specialized engineering services company with deep expertise in pre-silicon and post-silicon design and verification. We deliver end-to-end semiconductor and embedded system solutions covering RTL Design, SystemC Modeling, Emulation, Design Verification (DV), Physical Design (PD), Design for Testability (DFT), and Pre- & Post-silicon Validation — helping clients achieve faster, more reliable product development. Headquartered in Hyderabad, with offices in Bangalore and Raipur, and supported by our skilled engineering teams in Malaysia, we serve global clients through flexible engagement models like Time & Materials (T&M), Offshore Development Centers (ODC), Subcontracting, and Build-Operate-Transfer (BOT). Our expertise spans VLSI and Embedded Systems, with a strong focus on Wireless, IoT, and Automotive domains. We also work on advanced technologies including HBM3/3E workloads, AI/ML, GenAI/LLMs, and edge computing. At Silicon Patterns, we’re committed not only to technical excellence but also to maintaining a strong work-life balance for our teams because great engineering starts with well-supported people.Websitehttps: