Job Title

Hiring: DFT Lead | 7+ Years Experience | Semiconductor/VLSIKey ResponsibilitiesLead end-to-end DFT implementation at block and top level (SCAN, MBIST, LBIST, BSCAN, IJTAG)Perform hierarchical scan insertion and manage complete ATPG flow including coverage analysis and debugDrive MBIST integration and RTL-level DFT verificationConduct LBIST coverage analysis and enable gate-level simulation (GLS)Define and implement IEEE 1149.1 JTAG & IJTAG architecturesPerform DFT verification, lint checks, and equivalence checksDevelop ATE patterns, support silicon bring-up, and post-silicon debugDefine integration and test strategy for Analog IPsCollaborate closely with RTL, Physical Design, and Verification teamsManage multiple designs and ensure high-quality tape-out deliveryQualificationsB.E./B.Tech/M.E./M.Tech in ECE, EE, VLSI, Computer Engineering, or related disciplines6+ years of hands-on DFT experienceStrong expertise in SCAN, MBIST, LBIST, BSCAN, IJTAG, and IP test modesProficiency with EDA tools such as Tessent, Genus, Fusion Compiler, VCS, Conformal/Formality, SpyGlassStrong ATPG coverage analysis, DFT debug, and verification skillsScripting expertise in Perl, TCL, and/or PythonExcellent leadership, communication, and cross-functional collaboration skills