Job Title

Responsibilities: Independently handling Block level PnR implementation with industry-standard tools. Responsible for planning and executing all aspects of Physical Design including Synthesis, Floor planning, Place and Route, Clock Tree Synthesis, IP integration, Extraction, Physical Verification, and taking blocks to closure. Ownership of digital sub-blocks/chip level (specification and implementation). Definition of new test cases similar to product definition and for designing significant blocks of chip, including chip architecture and chip top integration, with a focus on improving Quality of Design System. Develop and execute QA test plans, verification methodology & test strategies for analog block/chip level to maximize the coverage of features/methodology supported in the technologies/Design Flows. Responsibility for the setup and running of test cases, analyzing failures, and bug fix validation and verification by analyzing all device models/components in the technology and ensuring ~100% coverage in the test plan/test cases. Work with design team/product team in generating test plans and closure of code and functional coverage. Analyze key coverage metrics collected, build regression status reporting dashboard, and come up with missing test cases. Responsible for automation of manual processes (including design flow/design package qualification mechanisms, generation of test reports/dashboards, etc.) and providing automation requirements for reducing manual steps in qualification. Working in compliance with Quality/Process standardsRequirements Strong understanding of the RTL2GDSII flow or design implementation in leading process technologies. Proficiency in Python, Tcl and Perl scripting is preferred. Must have hands-on experience in all stages of design synthesis, floor planning, placement, CTS, routing, crosstalk avoidance, and physical verification. Strong knowledge and experience in standard place and route flows; ICC2/Synopsys and Innovus/Cadence flows preferred. Must have knowledge of Physical verification, Extraction, SDF generation, PrimeTime, Multi-mode multi-corner optimization, EM/IR drop analysis, and low power techniques (UPF knowledge). Block level PnR implementation in technologies with feature sizes of 90nm, 65nm, 40nm, 22nm, and 12nm or lower technology nodes. B.Tech or M.Tech in Electronics/Electrical Engineering/VLSI 2-4 years of strong Digital Design Engineer Experience