Key Responsibilities Develop and maintainSystemVerilog/UVM-based verification environmentsfor IP/SoC-level designs Performprotocol-level verificationforPCIe Gen 5+andUCIe Defineverification plans , coverage models, and test scenarios Develop reusable testbenches, sequences, drivers, monitors, and scoreboards Analyze functional coverage, debug failures, and close coverage Work closely withdesign, architecture, and validation teamsto ensure protocol compliance Support regression execution and issue triage Ensure verification quality, completeness, and on-time deliveryExperience required 5+ yearsof hands-on experience inDesign Verification Strong proficiency inSystemVerilog and UVM Protocol verification experience is mandatory Hands-on experience withPCIe Gen 5 or above Experience withUCIe protocol Excellent debugging and problem-solving skillsEducational Qualification B.E./B.Tech or M.E./M.Tech in Electronics / Electrical / Computer Engineering or related field
Job Title
Senior Design Verification Engineer