Location: Hyderabad Notice Period: 0 to 45 Days 5+ yearsof hands-on experience inASIC/SOC physical design . Strong expertise inAMD physical design flowand signoff tool chain. Proficiency in: Floorplanning, placement, CTS, routing Multi-mode multi-corner (MMMC) timing closure IR/EM analysis CLP/VCLP/FEV analysis Power/Clock/domain partitioning Experience with signoff tools likeFusion compiler, PrimeTime, RedHawk, Calibre . Expertise in scripting languages:Tcl, Perl, Python . Deep understanding of sub‑7nm design challenges (congestion, variability, advanced timing methodologies).
Job Title
Physical Design Engineer