Physical Design Lead Locations:Bangalore Experience:10–16 Years (VLSI Physical Design) About the Role We are looking for a highly experiencedPhysical Design Leadto own top-level physical implementation and integration of large-scale SoC and ASIC platforms. In this role, you will drive hierarchical integration strategy from netlist to GDSII, ensuring world-class PPA (Power, Performance, Area) and signoff quality across complex, multi-block designs. You will operate at the center of architecture, RTL, IP, DFT, packaging, and signoff teams—leading execution, shaping methodology, and delivering first-pass silicon success on advanced technology nodes. What You’ll Do End-to-End Physical Integration Owntop-level hierarchical physical designfrom netlist through tapeout Define and drivefloorplanning, partitioning, and integration strategyfor large SoCs Integrate CPUs, accelerators, memory subsystems, analog/hard macros, and third-party IP Lead top-levelplacement, CTS, routing, and physical optimization Resolve congestion, cross-block interactions, and integration challenges Timing, Power & Signoff Excellence Drivetop-level timing closureincluding complex inter-block paths Ownpower planning and power integrity (IR/EM) closure Addresssignal integrity, noise, and crosstalkissues Ensure readiness for: STA Physical Verification (DRC/LVS) Reliability and signoff Cross-Functional Leadership Partner with RTL, architecture, IP, DFT, packaging, and signoff teams Provide early physical feedback to influence micro-architecture decisions Review block-level constraints, floorplans, and PD quality metrics Align integration strategy with product performance and schedule goals Technical Ownership & Mentorship Lead and mentor block-level PD teams across multiple design partitions Define scalablehierarchical PD flows and best practices Drive methodology improvements for quality, runtime, and predictability Lead design reviews and technical risk mitigation Program Execution Own top-level integration milestones and delivery commitments Communicate risks, trade-offs, and status clearly to stakeholders Support customer reviews and tapeout readiness checkpoints Required Qualifications Bachelor’s or Master’s degree in Electrical/Electronics Engineering or related field 10–16 years of hands-on experiencein physical design and SoC integration Strong expertise inhierarchical physical design of large SoCs Deep understanding of: Floorplanning & partitioning CTS & routing Timing closure IR/EM & signal integrity Physical verification & signoff Extensive experience with industry tools such as: Cadence Innovus Synopsys ICC2 PrimeTime / Tempus Strong scripting skills inTcl, Perl, and/or Python Proven leadership, communication, and execution skills Preferred Qualifications Experience onadvanced nodes (7nm, 5nm, 3nm, 2nm) Exposure to2.5D/3D IC and advanced packaging technologies Prior customer-facing or technical delivery ownership Experience with very large multi-die or high-performance compute SoCs Why You’ll Love This Role Own physical integration of next-generation silicon platforms Influence architecture and product quality at massive scale Work on cutting-edge process technologies and packaging innovations Lead complex designs that power AI, cloud, networking, and compute systemsAbout Us: Silicon Patterns is a specialized engineering services company with deep expertise in pre-silicon and post-silicon design and verification. We deliver end-to-end semiconductor and embedded system solutions covering RTL Design, SystemC Modeling, Emulation, Design Verification (DV), Physical Design (PD), Design for Testability (DFT), and Pre- & Post-silicon Validation — helping clients achieve faster, more reliable product development. Headquartered in Hyderabad, with offices in Bangalore and Raipur, and supported by our skilled engineering teams in Malaysia, we serve global clients through flexible engagement models like Time & Materials (T&M), Offshore Development Centers (ODC), Subcontracting, and Build-Operate-Transfer (BOT). Our expertise spans VLSI and Embedded Systems, with a strong focus on Wireless, IoT, and Automotive domains. We also work on advanced technologies including HBM3/3E workloads, AI/ML, GenAI/LLMs, and edge computing. At Silicon Patterns, we’re committed not only to technical excellence but also to maintaining a strong work-life balance for our teams because great engineering starts with well-supported people. Website https:
Job Title
Lead Physical Design Engineer