Job Title

Proxelera is India’s premium chip and system software product engineering partner. Our engineers take extreme passion in your assignments and deliver through their years of high quality experience to make your product successful. We understand the challenges of all aspects of product engineering – right from design planning stage to post silicon work. We also offer you unparalleled quality of service in productization of your chip through reference system design and system software development.Job Description:RTL Design Engineer Experience: 4–6 Years Location: BangaloreJob Description Strong RTL coding in Verilog/SystemVerilog is non-negotiable, this is a pure RTL design role. Own block-level RTL development from micro-architecture to clean, synthesizable RTL. Design FSM/FSMD, apply pipelining, and optimize RTL for timing and performance. Hands-on execution and closure of Lint, CDC, X-prop, and structural checks. Debug RTL vs synthesis mismatches and functional issues. Work closely with DV teams to resolve design bugs efficiently. Solid understanding of logic synthesis and constraint intent at block/top level. Support timing closure in collaboration with PD and STA teams. Exposure to pipelined processor architectures (ARM or RISC-V preferred). Maintain clear documentation of RTL changes and design decisions.