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Job Title:Analog Layout Engineer – Advanced / Lower Nodes (TSMC) Experience:4 -7 Years Location: Hyderabad (F2F)Job Summary We are seeking an experienced Analog Layout Engineer to design and implement high-performance analog and mixed-signal IC layouts in advanced CMOS technology nodes (e.g., 28nm, 16nm, 7nm, 5nm, 3nm) at TSMC. The role requires close collaboration with analog design, verification, and foundry teams to ensure robust, manufacturable, and high-yield layouts. Key Responsibilities Design and deliverfull-custom analog and mixed-signal layoutsfor advanced TSMC technology nodes Handle layout of blocks such asLDOs, PLLs, ADC/DACs, SerDes, amplifiers, bandgaps, clocking, and IOs Applyadvanced layout techniques : Matching, symmetry, common-centroid, interdigitation Guard rings, shielding, substrate isolation EM/IR-aware routing and reliability-driven layout Ensure compliance withTSMC DRC/LVS/DFM rules , including advanced node-specific constraints Addressparasitics, coupling, noise, and variabilitychallenges in lower nodes PerformPEX extractionand support post-layout simulation and silicon debug Work closely with analog designers to optimize layout forperformance, yield, and reliability Interact with TSMC foundry teams forrule clarifications, waivers, and silicon issues Required Qualifications Bachelor’s or Master’s degree inElectrical Engineering or related field 5+ yearsof hands-on analog layout experience (less for junior roles) Strong experience inTSMC advanced nodes (≤28nm preferred) Expertise withCadence Virtuosolayout environment Solid understanding ofdevice physics, matching, and layout-dependent effects (LDE) Proven ability to handlecomplex DRC and advanced node constraints Preferred Qualifications Experience withFinFET nodes (16nm/7nm/5nm/3nm) Familiarity withEM/IR, antenna rules, and reliability analysis Experience inhigh-speed or low-noise analog designs Tape-out experience onmultiple TSMC advanced nodes Knowledge ofDFM, yield enhancement, and silicon correlation