Hiring | RTL Design Engineer ACL Digital is looking forRTL Design Engineerswith strongmicro-architectureexperience to join our growing VLSI teams. Experience:4+ years Strong hands-on inRTL Design (Verilog/SystemVerilog) Solidmicro-architectureunderstanding Experience inLint & CDC(SpyGlass / Questa / VC CDC or similar) Notice Period:Immediate to 30 days / Serving notice periodInterested candidates, share your resume at:kalavathi.srinivas@#RTLDesign #MicroArchitecture #RTLJobs #Lint #CDC #VLSI #ASIC #SoC #SemiconductorJobs #HiringNow #ImmediateJoiners #ACLdigital
Job Title
Senior/ Lead RTL Design