Job Title

We are looking for an experiencedSenior Architecture Leaderto define and drive next-generationMCU chiplet architecturesandDie-to-Die (D2D) interface IPs . This role offers a chance to work at the intersection of system architecture, microarchitecture, and cross-functional execution. Key Responsibilities Define and drivechiplet architectureoptimized for MCU constraints Lead architecture ofD2D interface IPs(UCIe / Bunch-of-Wire) Collaborate closely withproduct and software architects Shapemicroarchitectureof IP blocks and subsystems Work withverification teamson test-plan development and reviews Collaborate withDesign, Validation, DFT, Physical Design, and Emulation teams Supportpost-silicon debugand functional validation DriveIP selection and make/buy decisions Qualifications & Experience BTech / MTech inEE / ECE / Computer Engineering / Computer Science 15+ yearsof hands-on hardware architecture experience Strong communication, problem-solving, and teamwork skills Experience withD2D protocols(UCIe, Bunch-of-Wire) Expertise inMCU/Microprocessor architecture , interconnects, cache coherency Experience benchmarking and tuningIP/SoC performance Strong knowledge ofAHB/AXI/CHI , memory systems (ROM, RAM, Flash, LPDDR/DDR3/4) Deep understanding ofclocking, power management, system modes, debug, security Good to Have NIC / FlexNOC interconnect experience Flash memory subsystems Power management architecture Virtual Prototyping tools:ARM Fast Models, Synopsys Virtualizer, Wind River SIMICS What We’re Looking For Acan-do attitudeand openness to diverse teams and cultures Passion for building scalable, high-performance architectures