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Job Role : Lead DFT EngineerJob Location : HyderabadExperience : 6 to 12 yearsPreference : Immediate to 30daysRequirements:Strong fundamentals in digital logic design and DFT Architecture conceptsProficiency in HDL languages (Verilog / VHDL) for RTL design and analysisSolid understanding of VLSI testing principles, including fault models and DFT methodologiesHands-on experience with DFT implementations - Scan Compression at IP level, Scan Retargeting at SoC level (Knowledge of SSN is good-to-have)Experience with industry-standard DFT and test tools, such as: Tessent TestKompress, Tessent Diagnosis, MBIST tools, RTL and gate-level simulation environmentsWorking knowledge of FPGA architectures, design and synthesis flowsFamiliarity with Linux-based development environmentsScripting skills (Perl,TCL,Python) for automation and productivity enhancement are a strong plusQualification:Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering or a related field is preferred.Formal education or training with a focus on digital design, DFT or test methodologies is desired.Tessent Scan, ATPG or MBIST certifications are a plus.Apply here or share cvs to