Location: HyderabadNotice Period: 0 to 45 Days5+ years of hands-on experience in ASIC/SOC physical design.Strong expertise in AMD physical design flow and signoff tool chain.Proficiency in:Floorplanning, placement, CTS, routingMulti-mode multi-corner (MMMC) timing closureIR/EM analysisCLP/VCLP/FEV analysisPower/Clock/domain partitioningExperience with signoff tools like Fusion compiler, PrimeTime, RedHawk, Calibre.Expertise in scripting languages: Tcl, Perl, Python.Deep understanding of sub‑7nm design challenges (congestion, variability, advanced timing methodologies).
Job Title
Physical Design Engineer