Job Title

Senior Physical Verification EngineerLocation: Hyderabad, IndiaExperience: 3–4 YearsNotice Period: Immediate to 15 Days (Mandatory)Education: B.Tech/M.Tech in Electronics, Electrical Engineering, or VLSI.Role ObjectiveAs a Physical Verification (PV) Engineer, you will be responsible for ensuring the physical integrity and manufacturability of complex SoCs and high-performance digital blocks. You will work on cutting-edge process nodes (7nm, 5nm, and below), driving sign-off convergence through rigorous DRC/LVS analysis and cross-functional collaboration.Key ResponsibilitiesRole: Execute and debug DRC, LVS, and ERC sign-off at the block and full-chip levels using industry-standard tools like Calibre or ICV.Core Tasks: Identify and resolve complex layout issues, including connectivity shorts, antenna violations, and density requirements on advanced process nodes (7nm/5nm).Collaboration: Work closely with Physical Design and Layout teams to drive design convergence and ensure tape-out readiness.Technical Skills RequiredIndustry-Standard Tools:Expertise: Mentor Graphics Calibre (nmDRC, nmLVS, PERC).Proficiency: Synopsys ICV (In-Design / Sign-off) or Cadence Pegasus.PnR Interaction: Familiarity with Innovus or ICC2/Fusion Compiler to understand physical implementation gaps.Technical Knowledge:Deep understanding of Foundry Design Manuals (TSMC, Samsung, or Intel Foundry).Solid grasp of semiconductor physics, CMOS layout, and parasitic extraction (PEX).Knowledge of dummy metal fill, slotting, and guard-ring requirements for advanced nodes.Scripting: Proficiency in Tcl, Perl, or Python for automation. Ability to write or modify Calibre SVRF/TVF code is a major plus.Soft Skills & QualificationsImmediate Availability: Must be able to join within 0–15 days.Problem Solving: Proven ability to debug /"hard-to-find/" shorts and opens in massive SoC databases.Communication: Strong verbal and written skills for reporting sign-off status and risks to stakeholders.