Job Title

Location: Bengaluru, India Experience: 10–15 years Industry: Semiconductors | AI | Networking | ASIC DesignRole OverviewAs the Synthesis & LEC Lead , you will be the bridge between high-level RTLarchitecture and physical reality. In the world of high-performance AI SOCs, the /"RTL-to-Netlist/"phase is where performance is won or lost. You will hold end-to-end ownership of logical andphysical synthesis, and formal verification, ensuring our chips achieve industry-leading Power,Performance, and Area (PPA) targets while maintaining 100% logical integrity.Key ResponsibilitiesSynthesis & PPA Optimization● End-to-End Ownership: Define and drive the synthesis strategy, from initial RTLhandoff through complex gate-level netlist generation and timing closure.● Low-Power Implementation: Drive front-end low-power optimization using UPF,ensuring sophisticated power-gating and multi-voltage strategies are implementedflawlessly.● PPA Leadership: Collaborate closely with RTL, DFT, and Physical Design teams tosqueeze every bit of performance and area efficiency out of the design during theRTL-to-Netlist transition.Formal Verification & Sign-off● Logical Equivalence (LEC): Own the formal verification flow, with hands-on expertise inConformal Low Power to ensure functional consistency across synthesis andlow-power insertions.● Analysis & Debug: Drive signal integrity (SI) and noise analysis flows to ensure robustnetlist quality before handing off to the Physical Design team.Key Skills & Technical Requirements● Synthesis Mastery: Deep knowledge of both logical and physical synthesis flows(Topographical/Physical-aware synthesis).● Tool Proficiency: Expert-level experience with Cadence or Synopsys suites, specificallyGenus, DC, Tempus/PrimeTime, and Conformal.● Formal Verification: Proven track record in LEC, specifically handling complexlow-power structures and multi-voltage domains.● Timing & SI Expert: Expert-level understanding of MCMM timing closure, signalintegrity, and the impact of cross-talk on high-speed AI paths.● Architecture Awareness: Good understanding of scan architecture, DFT modes, andPnR methodologies to ensure synthesis is /"DFT-friendly/" and /"Place-friendly./"● Scripting: Proficiency in Tcl and Python to automate synthesis and timing analysispipelines.Technical Leadership & Background● Mentorship: Actively mentor junior engineers, establishing best practices for constraintdevelopment and front-end flows.● Project Management: Work with the Project Lead to define execution schedules, trackprogress, and proactively manage technical risks during the tape-out cycle.● Education: Bachelor’s or Master’s degree in Electrical/Electronics Engineering or arelated field.● The Startup Mindset: Ability to build high-quality front-end flows from scratch in a lean,fast-moving environment.