Design Verification EngineerExp- 4 to 10 yrsLocation- Bangalore/HyderabadNP should be 0-30 daysEducational Qualification: M.S./M.Tech, BS/BE (Electronics)Roles & Responsibilities:• To be part of a highly skilled ASIC Team working on the newest technology nodes• Responsible for overall IP/Block and sub-system verification from test plan creation, System Verilog/UVM testbench development to signoff• Ensure first pass product through verification coverage and sign-off criteria• Mentoring and coaching junior team members• Pair with similar domain specialists across other geographical locations on core technical initiativesRequired Skills:• Should have expertise in IP/Block/Subsystem level verification, should be expert in System Verilog and UVM methodology. • Proven track record of building test plan, UVM Environment and test benches• Experience with RTL debugging, scoreboard, assertions, functional coverage coding and code coverage analysis• Sound knowledge of Verilog and System Verilog languages, AXI/AHB protocols.Interested candidates can share resume to
Job Title
Senior Design Verification Engineer