Job Title

Job SummarySeeking an Analog Design Engineer with 5–10 years of experience in high‑speed I/O circuit design to develop high‑performance analog and mixed‑signal IPs. The role involves architecture definition, circuit design, simulation, and silicon validation for advanced‑node high‑speed interfaces.Key ResponsibilitiesWork on High‑Speed I/O and SerDes PHY design, including PLLs, CDRs, equalizers, and multi‑Gbps analog blocks.Design/optimize TX/RX front‑ends, PLL/DLL/CDR circuits, equalization (CTLE/DFE/FFE), and bias/termination/ESD structures.Lead block‑level architecture and circuit development for high‑speed I/O subsystems.Run transistor‑level simulations (AC, transient, noise, jitter, BER).Handle pre‑layout and post‑layout verification with parasitic extraction.Address signal integrity issues such as channel loss, crosstalk, and reflections.Support layout floorplanning and reviews; collaborate with digital, physical design, packaging, and system teams.Participate in silicon bring‑up, lab testing, and debug.Ensure spec compliance and PVT robustness; mentor junior engineers.Required QualificationsBachelor’s or Master’s in Electrical Engineering or related field.5–10 years of analog/mixed‑signal design experience.Strong background in high‑speed I/O design in CMOS.Knowledge of jitter, noise, BER, signal integrity, and channel modeling.Proficiency with SPICE tools (Spectre, HSPICE, Eldo).Strong understanding of CMOS device physics and PVT variation.Experience in advanced technology nodes; able to work independently with strong ownership.