Job Title

We are looking for a Physical Design Engineer to work on end‑to‑end ASIC/SoC block implementation.Key Responsibilities:Handle floorplanning, timing constraints, synthesis, formal verification, clock tree, routing, extraction, and timing closure.Work on block‑level Place & Route from netlist to GDS.Partner with design teams to troubleshoot issues and suggest improvements.Manage timing budgeting across teams and ensure accurate STA closure for all corners and modes.Independently generate ECOs and ensure sign‑off quality for DFT, signal integrity, physical verification, and DFM.Experience: 4+ yearsLocation: Hyderabad/Bangalore/Noida/Ahmedabad/Pune/Chennai (On-site only)Role: Physical Design Engineer