Job Title

Job Title: Formal Verification EngineerExperience: 3+ YearsLocation: Bangalore / Hyderabad / Noida (or as per requirement)Employment Type: Full-timeJob Summary:We are looking for a Formal Verification Engineer with 4+ years of experience in semiconductor verification. The candidate will be responsible for performing formal property verification of RTL designs to ensure functional correctness and improve overall verification coverage.Key ResponsibilitiesDevelop and execute formal verification strategies for complex digital designs.Write SystemVerilog Assertions (SVA) and properties for formal verification.Use formal verification tools to identify design bugs and ensure functional correctness.Analyze RTL design and verification results to identify corner-case issues.Work closely with design and verification teams to debug and resolve issues.Perform coverage analysis and closure using formal verification techniques.Support verification sign-off activities for IP and SoC level designs.Create documentation for verification methodology, results, and bug reports.Required SkillsStrong knowledge of Formal Verification methodologies.Experience writing SystemVerilog Assertions (SVA) and properties.Hands-on experience with formal verification tools such asSynopsys VC FormalCadence JasperGoldOneSpin / Siemens Formal toolsStrong understanding of RTL design using Verilog/SystemVerilog.Experience in debugging RTL issues using formal analysis.Good understanding of digital design concepts and verification flows.Experience working in Linux/Unix environments.Scripting knowledge in Python, Perl, or Shell is a plus.Preferred SkillsExperience in SoC/IP level verification.Knowledge of UVM-based verification environments.Understanding of low power verification or CDC/RDC verification.Familiarity with protocols such as AMBA (AXI, AHB, APB).EducationB.E / B.Tech / M.E / M.Tech in Electronics / Electrical / VLSI / Computer Engineering or related field.