Job Title

TITLE: PCB Layout Design Engineer(Principal/Senior Staff Engineer)LOCATION: GREATER BENGALURU AREACompany DescriptionWe are looking for exceptional talent and leadership to join Fast Growing Startup into Scalable Intelligence, the world’s first company developing Agentic Silicon for powering the future of AI.Founded in 2023, We have deep customer engagements across America, Europe, and Asia, and demonstrated functional prototypes to prove our concept and vision.Job DescriptionSeeking Senior PCB Layout Design Engineers who will own the physical design of complex, high-speed PCBs from initial stack-up definition through final fabrication release -collaborating with Systems, SI, PI and mechanical engineers to deliver manufacturable boards. Key responsibilitiesLead end-to-end layout for multilayer boards (>10 layers) supporting High speed Serdes Interface(upto 224G) and High power solutions(KW)Create and Maintain footprints in the library and validateFeasibility studies for various system and board configurations and identifying the tradeoffsDefine HDI stack-up co-optimization balancing between SI and PI requirementsPerform constraint-driven routing of critical nets — length matching, differential pair tuning, via stub minimizationCollaborating with Package designer in definition and optimization of the ballmapCollaborate with Systems, SI, PI, Packaging and Mechanical EngineersDrive DFM/DFT reviews with contract manufacturersRequired qualifications10+ years of professional PCB layout experience on high-speed Serdes designs and high powerDeep proficiency in Cadence Allegro toolProven hands-on experience defining the HDI stack-up and designing HDI boards with blind/buried viasDemonstrated expertise in symbol and footprint generation from ScratchSolid understanding of SI design: Breakout, Via stubs, Loss, xtalk and impedance requirementsSolid understanding of PDN design: decoupling solution, Power stage and inductor design, Isolation requirementsB.S. in Electrical Engineering, Electronics Technology, or equivalent demonstrated experiencePreferred qualificationsWorked on PCIe Gen6/7 and 112G/224G Ethernet interfacesFamiliarity with OCP / Open Rack (ORV3/ORW) form factors for datacenter board designsUnderstanding of the various connector solutions for high speed SerdesHands-on experience working from the start to the finish of the PCB designToolsCadence Allegro , Siemens Xpedition SchematicContactSumit S. B/"Mining the Knowledge Community/"Practice Head(Talent Acquisition. Semiconductors Domain)