Job Title

Digital Design Engineer Experience: 8+ YearsResponsibilities Architect, design, and verify complex digital front-end circuits and systems for FPGA and ASIC implementations, including defining digital design requirements, developing architectural specifications, and coding high-quality HDL modules that meet performance, reliability, and scalability targets.Execute all assigned tasks with a strong focus on reusability, efficiency, and area-optimized design.Lead/participate in comprehensive design reviews, providing clear, constructive feedback to enhance design robustness, quality, and development efficiency.Apply mixed-signal understanding (is a strong plus) to ensure smooth integration of digital front-end architectures with analog and mixed-signal components.Proactively define optimal system and component-level concepts, driving digitization initiatives in close collaboration with engineers from all relevant disciplines.Collaborate with cross-functional engineering teams (eg. application and system engineers) to establish cost-effective solutions that meet functional, performance, and architectural objectives.Provide technical guidance and mentorship during reviews and technical discussions, contributing to a culture of engineering excellence.Continuously refine and enhance digital design methodologies, development workflows, and toolchains to increase productivity and design consistency.Create and maintain comprehensive digital design documentation, including requirements, architecture descriptions, design specifications, and block-level details.Document and/or review design processes, verification strategies, test plans, and results in compliance with industry standards and best practices.Required Qualifications Master’s or PhD in Electronics Engineering or a related technical field with 6+ years of relevant experience, or a Bachelor’s degree with8+ years of experience in digital design, SoC integration, or ASIC digital architecture.Strong proficiency in hardware description languages (HDLs) such as Verilog and SystemVerilog or VHDL.Proven track record of delivering complex digital design projects and collaborating effectively across multidisciplinary teams.Deep expertise in ASIC and FPGA design methodologies, including front-end architecture and implementation flows.Working knowledge of UVM is a strong plus. Experience with Design for Testability (DFT) and Design for Manufacturing (DFM) practices, is a plus.Strong understanding of the digital design flow, including synthesis, simulation, static timing analysis, and related front-end development processes.Hands-on experience with formal verification tools, such as Siemens Questa Formal and Synopsys Spyglass.Good understanding of CDC (Clock Domain Crossing), RDC (Reset Domain Crossing), and multi-power-domain design techniques.