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Role: Design for Test (DFT)About Eximietas:Eximietas Design is a leading technology consulting and solutions development firmspecializing in the VLSI, Cloud Computing, Cyber Security, and AI/ML domains. Our successis anchored in the unparalleled expertise of our engineering leadership team, whosecollective experience spans renowned technology giants like Google, Cisco, Microsoft,Oracle, Uber, Broadcom, and Sun. With a strong commitment to innovation and excellence,we deliver cutting-edge solutions that empower businesses to thrive in the ever-evolvingdigital landscape.Experience:5 – 25 YearsLocations:Bangalore / Hyderabad / AhmedabadJob Description:We are seeking motivated Design for Test (DFT) professionals to join our growing team.Whether you are a hands-on technical lead or an industry veteran with architecturalexpertise, we offer roles that will challenge and grow your skills in advanced silicon testing.You will be responsible for the end-to-end DFT flow, from RTL to final pattern delivery, acrosscomplex IP, subsystem, and SOC designs.Core Responsibilities:● End-to-end ownership of the DFT implementation flow from RTL to final patternsign-off.● Scan architecture definition and implementation at RTL and gate level, including EDTand OCC.● Execution of block-level ATPG, DRC analysis, and coverage optimization.● Handling of pattern simulations, including both timing and non-timing simulations.● SOC-level integration, including pattern retargeting to subsystem and full-chip levels.● Integration, simulation, and debug of MBIST, IJTAG, and Boundary Scan (JTAG).● Independent debugging of DFT simulations and netlist-related issues.● Close collaboration with design, verification, and physical design teams to ensureDFT readiness.● Ownership of DFT sign-off activities and deliverables.Key Responsibilities:● Develop and implement robust DFT architectures for IP, subsystem, and SOC designs.● Perform scan insertion, ATPG generation, and pattern validation at block and toplevels.● Analyze and resolve coverage, DRC, and simulation failures to meet quality targets.● Define and execute DFT strategies aligned with project requirements and schedules.● Support pre-silicon and post-silicon test requirements.● Serve as the DFT point of contact for assigned projects, responsible for verificationand test readiness sign-off.Technical Requirements:Must-Have Skills:● Strong experience in netlist handling and ATPG simulations.● Proven expertise in block-level and SOC-level pattern retargeting and debug.● In-depth understanding of ICL and PDL standards.● Hands-on experience with at least one major DFT tool suite:o Siemens Tessento Synopsys TestMAX / TetraMAXo Cadence ModusPreferred & Advanced Skills:● Experience with Streaming Scan Network (SSN).● Knowledge of Analog and Mixed-Signal DFT methodologies.● Proficiency with SpyGlass for DFT linting and early-stage analysis.● Exposure to RTL-level DFT insertion and validation.● Strong scripting skills (TCL, Python, Perl) for automation.MBIST JDDFT MBIST Engineer – Job DescriptionCompany: Eximietas DesignLocation: Bangalore / HyderabadExperience: 4 – 10 YearsDomain: VLSI / Semiconductor / SoC