Job SummaryWe are seeking a skilled Physical Design Engineer with approximately 4 years of hands-on experience in the full-chip or block-level physical implementation of ASIC/SoC designs. The ideal candidate will have strong expertise in physical design flows, timing closure, and signoff activities for advanced technology nodes.Key ResponsibilitiesPerform block-level and/or full-chip physical design implementation including floorplanning, placement, clock tree synthesis (CTS), routing, and optimizationOwn timing closure across all implementation stages (pre-CTS, post-CTS, post-route)Handle congestion, IR drop, and power optimizationRun and debug DRC, LVS, and physical verification issuesPerform ECO implementation to address timing, power, and functional fixesWork closely with RTL, STA, DFT, and Signoff teams to resolve design issuesAnalyze and fix timing violations (setup, hold, DRV) across multiple modes and cornersSupport signoff checks such as STA, SI, IR/EM, and power analysisContribute to flow improvements, methodology documentation, and automation scriptsRequired Skills & Qualifications4+ years of experience in ASIC/SoC Physical DesignStrong understanding of PD flow:FloorplanningPlacement & optimizationCTSRoutingTiming closureHands-on experience with EDA tools, such as:Synopsys: ICC2, PrimeTime, StarRCCadence: Innovus, Tempus (or equivalent)Solid understanding of:STA concepts (setup, hold, OCV, AOCV, POCV)Low-power design techniques (clock gating, multi-Vt cells)Physical effects (IR drop, EM, crosstalk)Experience working on advanced nodes (28nm and below preferred)Good scripting skills in Tcl, Perl, or PythonPreferred QualificationsExperience with full-chip integration and top-level closureExposure to low-power signoff flows (UPF/CPF)Familiarity with DFT and scan-related physical constraintsExperience in high-frequency or low-power designsGood communication skills and ability to work in cross-functional teamsEducationBachelor’s or Master’s degree in Electronics / Electrical Engineering or related field
Job Title
Physical Design Engineer