Job Title

We’re expanding our Architecture & Modeling team at Lattice and are open to strong IC modeling talent across seniority levels. If you have experience in CMOS/transistor‑level modeling, FPGA fabric behavior, or PPA/architecture correlation, I’d love to connect.Lattice Semiconductor is looking for an IC Modeling Engineer to join our FPGA Architecture & Design organization. This role involves transistor‑level CMOS modeling, FPGA fabric behavior modeling, performance analysis, and architecture correlation across advanced technology nodes.You will work closely with architecture, RTL, circuit design, and CAD teams to build accurate models, validate design intent, and influence next‑generation low‑power FPGA architectures. While this position has senior‑level responsibilities, we are open to strong candidates across different experience levels who bring solid modeling fundamentals and a passion for FPGA architecture.Key ResponsibilitiesDevelop and maintain transistor‑level and circuit‑level models for FPGA logic, routing, memory structures, and core fabricPerform behavioral, electrical, and timing modeling to ensure correlation between architecture, RTL, and siliconImprove modeling methodologies including automation for PVT coverage, characterization flows, and simulation analysisAnalyze PPA trade‑offs and contribute to architectural exploration and optimizationCollaborate with Architecture, RTL, Circuit Design, and CAD teams to ensure modeling accuracy and integrationConduct competitive benchmarking and silicon‑level analysis to identify strengths, gaps, and improvement opportunitiesSupport LEC flows, design‑intent validation, and model correlation across multiple tool environmentsBuild and debug test‑chip prototype models and correlate simulation data with silicon measurementsCreate modeling specifications, documentation, and technical reports for cross‑team alignmentRequired Skills & ExperienceStrong expertise in transistor‑level CMOS modeling (HSPICE, Spectre, or equivalent)Hands‑on experience with FPGA fabric components such as LUTs, logic blocks, routing structures, wide adders, CRAM, or architecture explorationProficiency in automation and scripting (Python, Shell, Perl, etc.)Experience with RTL modeling (Verilog/SystemVerilog) for functional and correlation workflowsSolid understanding of PPA characterization, simulation methodologies, and PVT corner coverageFamiliarity with LEC flows, simulation automation, and mixed‑signal modelingStrong analytical and problem‑solving capability, with the ability to interpret silicon‑level dataPreferred QualificationsExperience range flexible; senior candidates preferred, but strong mid‑level profiles will also be consideredBackground in FPGA architecture, fabric logic design, or competitive architectural analysisExposure to test‑chip bring‑up, silicon debug, and architecture correlationAdvanced degree (MEng/PhD) in Electrical, Electronics, or Computer Engineering is a strong plus#ICModeling #CMOSDesign #TransistorModeling #FPGAJobs #SemiconductorJobs #ArchitectureDesign #ASICDesign #HSPICE #Spectre #RTLDesign #PythonScripting #ChipDesignCareers #HiringNow #LatticeSemiconductor