Job Title

We are seeking a highly skilled & motivated Chip Lead with 15+ years of experience to own the overall chip architecture and design executionLead multi-block design integrationManage handoff and sign-off of key stages: RTL freeze, synthesis, place & route, static timing analysis, and DFT.Drive IP integration, clocking strategy, power domain definitionCross-Functional CollaborationIdentify and mitigate design and schedule risksEngage with external IP vendors, EDA tool providersEducation/QualificationRequired - Bachelor’s in Electrical Engineering, Electronics, or Computer EngineeringPreferred - Master’s or PhD in VLSI Design, Microelectronics, or Computer ArchitectureCertifications - Not mandatory, but advanced coursework or certification in SoC design or project management is beneficialCompetence/CertificationsStrong background in:Digital IC design (RTL to GDSII)System-level architecture and IP integrationTiming closure (STA) and power-performance-area (PPA) optimizationUPF/CPF for low-power designFamiliarity with design for manufacturability, test (DFT), and silicon debug.