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Location: Greater Bengaluru Area (Hybrid)/ Greater Hyderabadwe are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable adoption. Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient. Unlike traditional interconnects, our solution reduces power consumption significantly while preserving high bandwidth and ultra-low latency — unlocking unprecedented efficiency for AI training and inference at scale. our architecture is not just an incremental improvement — it’s a foundational shift in how AI hardware is built for the future. Job Title: Principal MTS/Senior Principal Engineer VLSI Vertical: DFT & Test Logic Job Location: Hyderabad/Bangalore Job Type: Full-Time Job Summary: We are looking for a highly experienced and innovative Design for Test (DFT) Architect and Lead to drive test architecture and implementation for complex SoCs and ASICs. The ideal candidate will define and lead DFT strategy and infrastructure, enabling high-quality, production-testable silicon across advanced process nodes. This role involves close interaction with RTL, physical design, product engineering, and validation teams. Key Responsibilities: • Define and own the DFT architecture for complex SoC or ASIC designs targeting high test coverage and minimal area/power overhead. • Lead implementation of DFT features, including:  Scan insertion and compression (e.g., LBIST, MBIST, EDT/DFTMAX, Test Kompress)  Boundary scan (IEEE 1149.x)  JTAG infrastructure  Built-In Self-Test (BIST) for memories and logic  Test point insertion  At-speed testing (Launch-on-Capture, Launch-on-Shift) • Drive and automate ATPG vector generation, simulation, and verification. • Collaborate with RTL, synthesis, and PD teams to ensure DFT logic is synthesis-aware and timing-closure-friendly. • Integrate and validate DFT logic in pre & post-silicon environments. • Work with physical design and package/board teams to ensure full-chip DFT closure. • Lead DFT flow development and automation using scripting (TCL, Python, Perl). • Ensure full DFT signoff, including test coverage analysis (stuck-at, transition faults), pattern validation, and power-aware simulations. • Collaborate with test engineering to bring up silicon, correlate failures, and improve yield through efficient test strategies. • Support DFT bring-up on ATE, debug silicon issues, and enhance test robustness. • Evaluate and deploy next-generation DFT techniques, including hierarchical DFT, and 3DIC/chiplet test strategies. • Interface with EDA vendors on tool evaluations and flow improvementsRequired Qualifications: • Bachelor's or Master's degree in Electronics & Communication Engineering, VLSI Design, Microelectronics and Computer Engineering, or related field. • 18+ years of industry experience in DFT for ASIC/SoC. • Deep knowledge of DFT concepts, ATPG tools (e.g., Synopsys TetraMAX, Cadence Modus, Siemens Tessent). • Experience with memory BIST tools (MBIST Architect, Logic BIST, etc.). • Strong hands-on experience in RTL-level DFT insertion, verification, and debugging. • Familiarity with DFT constraints, scan stitching, and hierarchical test strategies. • Expertise in DFT and test pattern simulations, including power-aware ATPG and glitch-free testing. • Working knowledge of DFT-related standards (IEEE 1500, IEEE 1149.x). • Experience in Tapeout and post-silicon validation support. Preferred Qualifications: • Experience with DFT for chiplets, 2.5D/3D integration, or advanced packaging. • Familiarity with formal verification of DFT logic. • Experience with machine learning for test optimization. • Strong scripting background to automate flows and analytics.ContactUdayMulya Technologies/"Mining the Knowledge Community/"