Job Title

OverviewWe are seeking a highly skilled Senior Physical Design Engineer with strong hands-on expertise in Place & Route (PNR), Synthesis, and Signoff flows. The ideal candidate will have deep knowledge of timing closure, power analysis, and physical verification, along with exposure to low-power design methodologies (UPF).Key ResponsibilitiesExecute full-chip and block-level physical design including floorplanning, placement, CTS, routing, and optimizationDrive timing closure with a strong focus on Static Timing Analysis (STA)Manage signoff activities including:STA (Setup/Hold closure)Physical Verification (DRC/LVS)IR Drop and EM analysisPerform logic synthesis ensuring timing, power, and area targets are metConduct and analyze VCLP (Voltage-aware checks) and LEC (Logical Equivalence Check)Collaborate with RTL, DFT, and backend teams for design convergenceDebug and resolve timing, congestion, and power issuesImplement and verify low-power intent using UPFMandatory SkillsStrong hands-on experience in PNR (Place & Route) – MUSTExpertise in Static Timing Analysis (STA) – HIGH PRIORITYExperience in Synthesis and Signoff flows (STA, PV, IR/EM)Knowledge of VCLP / LEC flowsExposure to low-power design techniques and UPF