Job Title

About the Company We are seeking an experienced AMS Verification Engineer to develop models, build mixed‑signal verification environments, and execute co‑simulation and integration verification for high‑speed PHY IPs including DDR, HBM, UCIe, and SerDes. The role requires strong mixed‑signal methodology expertise, modeling skills, and hands‑on experience with both analog and digital simulation tools. About the Role We are seeking an experienced AMS Verification Engineer to develop models, build mixed‑signal verification environments, and execute co‑simulation and integration verification for high‑speed PHY IPs including DDR, HBM, UCIe, and SerDes. The role requires strong mixed‑signal methodology expertise, modeling skills, and hands‑on experience with both analog and digital simulation tools. Responsibilities Model Development Develop and enhance RNM, Verilog‑AMS, and SystemVerilog (wreal/RNM) models for AMS/PHY IPs. Create model validation plans and correlate behavioral models with SPICE simulations. Maintain model documentation, versioning, and modeling guidelines. Model‑Level Verification Build and maintain UVM/UVM‑MS based environments for standalone model verification. Develop assertions, checkers, coverage models, and achieve coverage closure. Create directed and constrained‑random stimulus for protocol/PHY features. Integration & Top‑Level Verification Integrate AMS models into subsystem and SoC‑level digital environments. Debug and resolve issues in timing, resets, power sequencing, and digital‑analog boundaries. Build mixed‑signal top‑level verification and co‑simulation configurations. Co‑Simulation & Sign‑off Set up and optimize Spectre/HSPICE/CustomSim with Xcelium/VCS/Questa‑ADMS co‑simulation flows. Establish SPICE‑vs‑behavioral correlation flows and golden reference checks. Drive regressions, triage failures, and generate debug reports. Automation & Collaboration Develop automation frameworks using Python/TCL/Shell/Make. Contribute to CI pipelines and revision control (Git/Perforce). Prepare technical documentation, reports, and present results to cross‑functional teams. Qualifications B.Tech/M.S. in Electrical Engineering, Electronics & Communication, or Computer Engineering. 5–8 years of AMS modeling and verification experience in IP/SoC environments. Required Skills Strong expertise in Verilog‑AMS, SystemVerilog (wreal/RNM), and UVM/UVM‑MS. Experience with mixed‑signal simulators: Digital: Xcelium, VCS, Questa Analog/SPICE: Spectre/APS, HSPICE, CustomSim, AFS/ADiT Proficiency with SVA, coverage methodologies, and mixed‑signal debug. Strong scripting experience (Python, TCL, Shell). Preferred Skills Experience with additional verification methodologies. Familiarity with advanced debugging techniques. Pay range and compensation package Compensation details will be discussed during the interview process.