Job Title

Project descriptionThe Platform Drivers team is on the lookout for a dynamic, energetic software engineer who can design, develop, and maintain clean and robust code. If you understand the intricacies of the Linux kernel and device drivers, this is the role for you. Join us!As a key contributor to the success of the client's IP, you will be part of a leading team to drive and enhance the client's abilities to deliver the highest quality, industry-leading technologies to market.ResponsibilitiesDesign and develop RTL IP blocks targeting AMD-Xilinx FPGA architectures, with emphasis on video connectivity subsystems.Contribute to system architecture, project definition, and implementation of low-latency video connectivity solutions.Perform RTL coding, integration, and documentation for modules specified independently or by cross-functional teams.Apply front-end design methodologies, including resource optimization, CDC (Clock Domain Crossing), and RDC (Reset Domain Crossing) handling.Collaborate across teams to ensure functional correctness, performance, and timely delivery of FPGA-based designs.SkillsMust have7-12 years of experienceMust have proven experience working on Video domain IPs / Digital IPs.Must have proven experience working with one or more protocols at the IP level: MIPI CSI / MIPI DSI / DisplayPort /HDMI / SDI.Hands-on experience with AMD/Xilinx FPGA device and Vivado toolchain.Hands-on experience with architecting/micro-architecture / detailed design from functional specifications.Hands-on experience with Synthesizable Verilog/ System Verilog RTL coding for FPGA designs.Lint, CDC, synthesis flow and static timing flows, formal checking, etc., experience.Working knowledge/experience in TCL, Perl, Python is an added advantage.SERDES architecture knowledge is a plus.Nice to haveHas a solid desire to learn and explore new technologies.Strong communication and presentation skills.Close collaboration with different teams across various time zones.