Job Title

Location: Bangalore Experience: 3-6 Years Job DescriptionWe are seeking a hands-on DFT Engineer / Senior DFT Engineer to drive DFT implementation for complex SoCs across the design cycle. This role requires strong execution capability, good technical judgment, and the ability to work independently on block/SoC-level deliverables while collaborating closely with design, PD, validation, and manufacturing teams.The ideal candidate is comfortable owning DFT tasks end-to-end (within a module or subsystem), with a strong focus on coverage, quality, and timely execution. ResponsibilitiesContribute to DFT architecture definition at block/subsystem level (scan, compression, MBIST, LBIST basics, boundary scan, test access)Drive RTL testability and support trade-offs across coverage, test time, power, and areaExecute scan insertion, stitching, and DFT DRC closureRun ATPG (stuck-at, transition, path delay), compression, and pattern optimizationSupport DFT signoff: coverage, pattern volume, test time, and basic power/timing considerationsDebug DFT issues across RTL, synthesis, P&R, and gate-level simulationsGenerate and analyze ATPG patterns; identify and close coverage gapsSupport silicon bring-up, failure analysis, and debug of scan/BIST/tester issuesWork with ATE/manufacturing teams for pattern validation and yield improvementDrive DFT ECOs and support methodology improvements Qualifications2–6 years of hands-on DFT experience with ownership of block/SoC-level DFT implementationAble to independently drive DFT tasks from insertion to sign-off with minimal supervisionStrong expertise in scan , ATPG, DFT DRC, MBIST , LBIST basics, JTAG/Boundary Scan, and low-power DFTGood debugging skills across DFT insertion, ATPG patterns, and coverage closureProficient in Cadence / Siemens (Mentor) DFT tool flowsStrong scripting skills (Tcl/Perl/Python) for automation and debugSolid understanding of RTL, Lint/CDC, low-power intent, and ASIC design flowAbility to collaborate effectively with RTL, PD, and STA teams to close DFT and coverage issues Soft SkillsStrong ownership mindset with ability to independently drive assigned DFT deliverablesStructured debugging approach across RTL, ATPG, scan/BIST, and silicon issuesClear communication of coverage metrics, risks, and progressAbility to manage multiple deliverables in a fast-paced environmentTeam-oriented mindset with willingness to learn and contribute