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About Proxelera:Proxelera is India’s premium chip and system software product engineering partner. Our engineers take extreme passion in your assignments and deliver through their years of high quality experience to make your product successful. We understand the challenges of all aspects of product engineering – right from design planning stage to post silicon work. We also offer you unparalleled quality of service in productization of your chip through reference system design and system software developmentJob Title: Sr. STA Engineer - 4-8YrsJob Location: Bangalore Job Overview:We are looking for a highly skilled Static Timing Analysis (STA) Engineer with strong expertise in synthesis and timing closure. The ideal candidate should have hands-on experience in logic synthesis, clock tree synthesis, and timing analysis using industry-standard EDA tools.Key Responsibilities:Perform Static Timing Analysis (STA) at block and full-chip levelWork on timing closure across all design stagesHandle Logic Synthesis and Clock Tree Synthesis (CTS)Analyze and fix setup/hold violations, timing bottlenecks, and path optimizationsCollaborate with design, physical design, and verification teamsGenerate and analyze timing reports, constraints, and sign-off checksEnsure timing convergence with PPA (Power, Performance, Area) targetsPreferred Qualifications:Experience with advanced technology nodes (e.g., 7nm/5nm is a plus)Knowledge of low-power design techniquesFamiliarity with scripting (Tcl, Python)Strong debugging and problem-solving skillsRequired Skills:Strong experience in:Logic SynthesisClock Tree Synthesis (CTS)Static Timing Analysis (STA)Hands-on expertise with tools:Cadence GenusCadence InnovusCadence TempusDeep understanding of:Timing constraints (SDC)Setup/Hold analysisMulti-mode multi-corner (MMMC) analysisTiming sign-off methodologie