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Job Description (IC Package Engineer) Position: Senior/Staff IC Package Engineer • Design Package layouts for multiple applications. • Able to handle constraints-driven IC Package layout methodology. • Having basic understanding on Signal integrity and power integrity concepts. • Conduct layout reviews with internal layout and design teams. • Release IC Package layout drawings to the various design teams and coordinates their layout activities by ensuring compliance with the Design rules. • Design Rules Check (DRC): Perform design rule checks to ensure that the layout meets the specific manufacturing and design guidelines. • Perform quality assurance by using CAM350 Gerber validation tools • Deliver Accurate layout designs by having basic Knowledge on Design for Manufacturing (DFM): Consider manufacturability and DFA : Craft for Assembly and DFT: Design for Testing. • Proven oral and written communication skills to connect with Customers and Multi-functional teams. EDUCATION, EXPERIENCE & QUALIFICATION REQUIRED • Bachelor’s degree in engineering (EEE/ECE ) with 3-9 yrs of IC packaging experience. • Proven ability in IC Package Layout Design. • Electronics fundamentals, Hands On experience on layout tools like Cadence APD 17.4, latest versions. Design guidelines, Constraint’s handling, Gerber generation and CAM 350, CAM validation. • Experience in routing high speed interfaces like PCIe, DDR memory interface, UFS, GPIO etc. • Must have shown understanding in SI (Signal Integrity) Routing guidelines. • Must have proven understanding in PI (Power Integrity) Routing guidelines. • Must have worked on Flip chip & Wirebond BGA’s. • Solid understanding on Highspeed Routing Guidelines. • Experienced in Mentor Hyper lynx DRC rules for Signal Integrity, Power Integrity tools, or similar is a plus. • Good Communication Social Skills, Excellent learning Problem solving ability.• Capable of working independently and as a team member, good attention to detail. • Excellent analytical skills and interpersonal proficiency.