Job Title

Role SummaryWe are looking for a highly experienced DFT Architect to define and drive end-to-end DFT architecture and flow methodology for next-generation silicon design programs. This role is focused on architectural ownership, methodology definition, and automation, rather than day-to-day vector execution.The candidate will play a critical role during the early phase of flow creation, working cross-functionally with design methodology, RTL, PD, and automation teams to enable faster and more efficient design cycles.Required Qualifications:8+ years (preferably 10+ years) of hands-on DFT experienceProven experience defining DFT architecture, not just executing DFT insertionBackground at end-to-end silicon companiesStrong understanding of:Scan, MBIST, DFT planning and quality metricsRTL (Verilog) – ability to write or review logic as neededExperience with Cadence DFT toolchains preferred(Synopsys experience acceptableDesired Skills:Strong EDA flow and methodology mindsetExperience automating constraints and flows from high-level specsFamiliarity with scripting (TCL, Perl, Python) is a plusAbility to work independently with minimal supervisionExcellent cross-functional collaboration skillsComfortable working in a global environment (IST hours with Japan overlap)Role Type & LocationLocation: India (Hyderabad preferred; Bangalore remote acceptable)Work Hours: ISTTravel: Occasional travel to Hyderabad may be required