Role - RTL Design/LeadLocation:EU / Remote Mandatory Skill:SoC Integrtion, IP integration RTL design & Coding RTL lint, RTL CDC Verilog / System Verilog Industry Experience : 5 to 10 yearsSoC Design engineer with experience working on SOCs based on ARM Architecture Should be familiar with AMBA based bus protocols like CHI, AXI, AHB, APB etc., Hands on experience in integration of PCIe and Ethernet Ips Good knowledge on design static checks like CDC, RDC, CLP etc., Hands on experience on chip IO integration Desirable to have working knowledge on GITTPBN1_UKTJ
Job Title
RTL Design/Lead