Job Title

Principal Design Lead EngineerAll potential candidates should read through the following details of this job with care before making an application.South EnglandThis is an exciting opportunity for a Principal Design Lead Engineer to join a fast-growing semiconductor and IP provider specializing in physical layer solutions for advanced wireless communications.As the Principal Design Team Leader, you will be working on 5G base stations on board satellites. The Principal Design Team Lead will take a leading role in shaping the technical roadmap to extend the power efficiency for the latest generation space qualified devices, and then delivering this technology to customers.You must have a proven track record of team leadership and delivering complex IP, who has a real interest in all aspects of the Intellectual Property development life cycle.This is a hands-on role requiring exceptional team leadership skills alongside technical skills to drive the design, quality, and delivery of Layer 1 IP. This role will play a pivotal part in the growth of the company and their product portfolio.Key ResponsibilitiesProvide strategic vision to inform technical decision-making and planning at a company level.Take responsibility for the successful and timely delivery of projects by providing technical leadership.Provide managerial leadership to build knowledge and support the team development.Work closely with the exec team to translate product requirements into hardware team deliverables.Implement designs targeting both FPGA and ASIC using industry standard techniques, including the creation of UVM based testbenches.Lead engineering methodology, processes and design techniques.Nurture professional growth of team members through regular mentoring, coaching, and feedbackSkills, Knowledge & Expertise:Track record of building and leading high performing collaborative teams.Expert knowledge of an RTL design (Verilog, SystemVerilog) for complex ASIC/FPGA products.A strong skillset in delivery of digital designs for ASIC and FPGA.Optimisation of timing and hardware resources for high throughput data or signal processing applications. Experience in power management techniques, synthesis and timing analysis.Understanding of UVM verification techniques or practical experience using UVM for IP verification.This is a Hybrid working role and you must be able to work onsite 2-3 days per week.For more info, please contact Rachel Mason at IC Resources.