Company OverviewDo not pass up this chance, apply quickly if your experience and skills match what is in the following description.Flux Computing designs and manufactures optical processors to train and run inference on large AI models. Join us in London to be part of a highly motivated and skilled team that thrives on delivering impact and innovation at speed.The roleWe are seeking aPhysical Layout Engineer to own the fullcustom layout of ultrahighspeed analog blocks that lie at the heart of the OTPU including: high speed DAC/ADC/TIAS, sub100fsrms jitter PLLs and large multi-lane clockdistribution meshes.You will translate transistorlevel intent into siliconaccurate geometry, balancing dense floorplans with the exacting parasitic, symmetry and matching constraints that highfrequency analog demands.ResponsibilitiesPlan, execute and signoff fullcustom layouts for highspeed analog/RF IP (TIAs, PLLs, CDRs, drivers, samplers, bias networks, ESD clamps).Drive floorplanning and toplevel integration, coordinating powergrid, clockmesh and microbump/flipchip escape routing so 100+ channels meet skew and returnloss targets.Perform parasitic extraction and EM/IR, thermal and electromigration analysis (Cadence Quantus / Calibre xRC, Voltus, EMX / HFSS), iterate with circuit designers to close speed, noise and phasenoise margins.Optimise critical paths for minimal capacitance and series inductance: shielded differential pairs, commoncentroid devices, guard rings, stitching vias and lowimpedance return paths.Ensure all blocks pass signoff: DRC, LVS, ERC, ESD, latchup, DFM and foundryspecific reliability checks.Collaborate with packaging and signalintegrity teams to codesign interposer, substrate and PCB breakouts; model bondwire / microbump parasitics in the extraction flow.Create and maintain layout guidelines, checklists and Skill/Tcl/Python automation scripts; mentor junior layout engineers and review their work.Skills & Experience7+years of custom analog/RF IC layout in production CMOS technologies, with multiple tapeouts that include >10GHz analog frontends or 56112Gb/s SerDes / CDR / PLL blocks.Expert user of Cadence Virtuoso custom layout tools plus signoff flows (PVS/Calibre DRCLVS, Quantus/StarRC, Voltus/RedHawk).Deep understanding of parasiticaware matching, device symmetry, shielding, differential routing, guardring strategy, ESD and onchip powergrid design.Demonstrated ability to close subpF capacitance budgets and
Job Title
Senior Physical Layout Engineer